DDR2 Registers and Buffers

Led by JEDEC, the memory industry has defined a new standard for memory modules called DDR2. The DDR2 modules will allow for faster memory access speeds while simultaneously reducing the power consumption of the memory modules.
The DDR2 modules compliant with the JEDEC specification can be either ‘unbuffered’ or ‘buffered’. As the data rates increase and the number of memory chips to be accessed is increased, the shape of the clock and address signals degrades. To clean up these signals, a ‘register’ is utilized to clean up the address signals and a ‘buffer’ cleans up the clock signal. Hence the term ‘buffered’ DIMM modules.
The buffer is a phase locked loop designed to lock on to the incoming clock signal and produce a clean waveform.

INPHI Registers and Buffers

Inphi’s DDR2 product story is rather remarkable in that INPHI is a new entrant to the register/buffer chip market segment, yet INPHI has produced a set of chips that outperform all others on the market.

Why are INPHI devices the best choice:
 - The INPHI buffers and registers exceed all of the pertinent JEDEC specifications
 - The INPHI devices consistently perform better than any competitors devices fielded to date.
 - The INPHI devices are made from 0.25 micron CMOS, thus the mask sets cost less, the cost of fabricating 0.25 micron die is less than 0.8 micron and there are many more fabs available to make the devices.
 - INPHI has designed the buffer chip to operate over all of the JEDEC frequency bands. Thus, a single die can be produced and then packaged for all the RAW Card configurations. Hence, the cost basis is further reduced and the savings can be passed through to the customers.

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